By Institution of Railway Signal Engineers (IRSE)

**Read or Download IRSE Green Book No.17 Track And Lineside Signalling Circuits in AC Electrified Areas (British Practice) 1962 PDF**

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**Extra info for IRSE Green Book No.17 Track And Lineside Signalling Circuits in AC Electrified Areas (British Practice) 1962 **

**Example text**

6) So, the total settling time is minimal when half the steps are done with delay A and half the steps are done with delay B. This does not depend on the resolution of the converter. 8) The ratio between the total DAC settling times is 3/4. 2 2 This assumes an even number of bits, for an odd number of bits the reduction is slightly lower, since the number of steps cannot be divided into two equally sized groups. 44 3 Sub-ADC Architectures for Time-interleaved ADCs Fig. 3 Left-hand side: basic configuration; right-hand side: configuration with overrange Although it can be attractive to use the scheme with variable settling times, for the remainder of this chapter the DAC settling time is assumed to be fixed, since the solutions presented in the next sections reduce the settling time even more and it is not useful to combine these with a variable settling time scheme.

7 Schematic for calculation of the optimum number of steps latter uses much less energy per conversion. This is true if either static or dynamic power consumption is dominant. Compared to the normal (1/8) overrange architecture commonly used in SAADCs [22], the single-sided overrange architecture uses 16% less static energy per conversion and 22% less dynamic energy per conversion. The conversion time for the conventional architecture is proportional to n2 , while for the converters with overrange, the conversion time is proportional to n.

For a longer track-time, more samplecapacitors are connected to the input at a time, limiting the input bandwidth. The second problem is that the virtual-ground cannot be maintained for highfrequency input signals. Except for over-sampling it is therefore not useful to deploy the described bottom-plate sampling technique in a time-interleaved T&H without a frontend sampler. The use of bottom-plate sampling in a time-interleaved T&H with a frontend sampler is considered next. When using a frontend sampler, it turns off before the switch in the T&H, see Figs.